It is necessary to interface a memory device into a system. This means that the memory and the surrounding system need to have matched logic high and low levels. Common interface levels are TTL, ECL and CMOS and the memory must be designed with inputs and outputs that shift from the levels of the internal circuitry to one of these external interfaces.
In conventional level shifters, rise delay and fall delay are quite different. This is illustrated in FIG. 1 for an inverting level shifter. As shown, when an input signal to the level shifter falls from high to low the output of the level shifter rises from low to high. The respective centered trip points for the two signals for this logic transition show that there is a fall delay of around 650 ps. However, when the input level rises and the output of the level shifter falls, the rise delay is only around 25 Ps. The difference between the rise delay and the fall delay, caused by the response of the level shifter, can be a problem in digital circuits where timing is important. This is particularly true of memory circuits where the rise delay and fall delay affect setup and hold times in a memory cycle.
A conventional approach to this problem is to use a ratioed logic delay chain which is designed to minimize the difference between the rise delay and the fall delay. However, this solution changes the response by adding a delay to both level transitions so that there is an additional and unnecessary increase in the fall delay. Such a delay chain is extremely sensitive and a great deal of care needs to be taken to centered the trip points of the associated logic.